A certain type of address decoder circuit for use in a semiconductor memory device such as a ROM or RAM device consists of decoder units of a number less than the number of the possible combinations of the bits forming an address signal to be supplied to the decoder circuit. A typical example of such a decoder circuit is the one used for a ROM device which is incorporated in a microprocessor to store microprogramming codes therein. Such a decoder circuit is directly responsive to the original input address signals so that, where each of the original input address signal consists of six bits, a maximum of 2.sup.6 =64 different combinations or sequences of bits could be used in the decoder circuit. In comparison with such a large number of possible decoder outputs, the decoder circuit actually has a far smaller number of outputs such as, for example, only twelve outputs and, for this reason, requires the provision of a disproportionately large number of active devices or transistors. Such a large number of active devices used in the decoder circuit inevitably results in correspondingly large amounts of capacitances provided by the diffusion regions of the individual active devices and accordingly in reduction in the switching speed achievable of the decoder circuit.
An address decoder circuit of the described type thus sometimes uses a predecode scheme for the purpose of reducing the number of the transistors to be used in the decoder circuit and thereby increasing the switching speed achievable of the circuit. The decoder circuit to implement such a scheme comprises a suitable number of 2-bit predecode circuits which are directly responsive to the original input signal bits. Each of these 2-bit predecode circuits is operative to predecode neighboring two of the original input address bits by producing a total of four different logic ANDs of the two bits and the inverted versions of the two bits. The predecoded signal bits thus produced by the 2-bit predecode circuits are used in some of the decoder units so that only one of the two original input address bits which have resulted in each of the predecoded signal bits is effective in the particular decoder unit with the other of the two bits virtually neglected from use. The result is accordingly that there exits address bits which are not used in the decoder circuit. Such a scheme of the decoder circuit inevitably results in irregularities in the geometrical topology of the decoder circuit fabricated on a semiconductor chip.
It is, thus, an important object of the present invention to provide an improved decoder circuit which is composed of a minimized number of active devices to achieve an increased switching speed of the decoder circuit.
It is another important object of the present invention to provide an improved predecode decoder circuit which effectively uses the original input address bits supplied to the decoder circuit.